1. Field of the Invention
This disclosure relates to the manufacturing of semiconductor memory cells, and more particularly, to a method of forming a storage node contact for an electrical connection of a storage node in a semiconductor memory such as a dynamic random access memory (DRAM) etc.
2. Description of the Related Art
A memory cell of DRAM is generally constructed of one access transistor and one storage capacitor. The capacitor may be classified either as a laminated type or a trench type dependent on where it is formed on a semiconductor substrate.
Semiconductor manufacturers that employs the laminated-type capacitor have been exploring ways to produce capacitors having a higher capacitance in a limited area in conformity with various requirements of semiconductor users. This research is driven by the high integration density of memory cells that produces a tightened critical dimension (CD), thereby decreasing the capacitance. However, in order to guarantee a refresh operating period within a range of regulated values, the capacitance is required to increase within the limited area.
As the integration level of a semiconductor memory gradually increases, a pattern size of the capacitor generally composed of a storage node as a lower electrode node and a plate node as an upper electrode gradually decreases. Thus, a bottom critical dimension (CD) of the storage node becomes too small to maintain an original pattern in a manufacturing process, in other words, the storage node collapses due to a leaning phenomenon.
In order to prevent the leaning phenomenon, a conventional method includes forming a straight type storage node on a lower structure formed in the straight structure to increase the bottom CD of the storage node or to lower a height of the storage node. However, with the former method it is difficult to increase the bottom CD when a design rule is first decided, and with the latter method it is difficult to obtain a desired capacitance.
As an advanced method to provide a larger bottom CD and reduce an occurrence of the leaning phenomenon within a limited area, the first method described above was recently improved. During formation of the storage node, an active region, a gate, a bit line contact, a storage node contact or buried contact, and bit line patterns are formed in a diagonal direction offset at an angle compared to the existing straight structure. Thus, a storage node of a square type is formed. This improved method increases the bottom CD of the storage node as compared with the storage node of the existing straight type, and this is known in this field as a diagonal structure. However, while the diagonal structure may increase the CD of the storage node to ensure stability, there are severe complications involved in forming a storage node contact that is properly connected to the storage node.
In order to solve this problem with the diagonal structure, another method of forming a square type storage node that combines the advantages of the straight structure and the diagonal structure was proposed. In this method, the active region, gate, bit line, and storage node contact, etc., are formed by the existing straight structure. Then, entirely thereon, a buffer layer is formed, and a pad contact is formed on the buffer layer, to thus connect a storage node of square type with a storage node contact formed in the straight structure. It is known in manufacturing the storage node of the square type that the bottom CD of the square type storage node is about twice as large as the storage node of the straight type based on the straight structure.
A contact forming method for an electrical connection of square-type storage node in the prior art will be described referring to FIGS. 1 through 6, as follows, only to provide a thorough understanding of the invention that will be subsequently described.
FIG. 1 is a plan diagram illustrating a disposition relationship between a storage node of a square type capacitor and contacts connected with the storage node in a semiconductor memory according to the conventional art. FIGS. 2 to 6 are cross sectional diagrams illustrating sequential processes in manufacturing the contact for a connection of the storage node referred to FIG. 1.
Referring first to FIG. 1, six word line stacks 8 as gates of a plurality of access transistors are formed in a first direction, and four bit line stacks 20 connected to drains of the access transistors are formed in a direction perpendicular to the first direction. Square type storage nodes 32 of the capacitors extend in a diagonal direction to the bit line stacks 20 and the word line stacks 8, forming an oblong structure. Herewith, a storage node contact 22 and a storage node contact pad 12 are overlapped as shown by the cross-hatched region. The storage node contact 22 and the storage node contact pad 12, and its lower part structure are formed by a straight structure as afore-mentioned. Further, a pad contact 26 formed through the buffer layer is partially overlapped with a portion at which the storage node contact 22 is formed. In the meantime, a reference number 15 indicates a bit line contact for connecting a bit line with a drain, and reference numeral 14 designates a bit line contact pad. FIGS. 2 to 6 are drawings taken along the lines A–A′ and B–B′ shown in FIG. 1.
On the left side of FIGS. 2 through 6, sectional views taken along an A–A′ cutting line direction of FIG. 1, namely, along a word line direction connected to a gate of an access transistor are each illustrated by a sequential process. On the right side of FIGS. 2 to 6, sectional views taken along a B–B′ cutting line direction of FIG. 1, namely, along a bit line direction connected to a drain of the access transistor are illustrated by a sequential process.
FIG. 2 illustrates a structure before forming a storage node contact in a DRAM based on a capacitor over bit line (COB) structure. A device separate layer 4 is formed on a predetermined region of a semiconductor substrate 2 to define a plurality of active regions. A gate oxide layer 8a is formed on the active regions. Thereon, a plurality of parallel word line stacks 8 traversing the active regions are formed. The word line stack 8 contains a word line 8b and a capping layer 8c laminated sequentially. An impurity ion is implanted into the active regions by using the word line stack 8 and the device separate layer 4 as an ion implantation mask, to thus form impurity regions 6s, 6d. The active impurity regions 6d between one pair of word line stacks 8 traversing the respective active regions are pertinent to common drain regions of a DRAM cell transistor. Further, the impurity regions 6s formed on both sides of each common drain region 6d are pertinent to source regions of the DRAM cell transistor. A word line spacer 8d is formed on a sidewall of the gate oxide layer 8a and the word line stacks 8. A first insulation layer 10 is formed on a face of the semiconductor substrate containing the word line spacer 8d. The first insulation layer 10 is partially etched to form the bit line contact pad 14 connected with the common drain region 6d and the storage node contact pad 12 connected with the source region 6s. Then, a second insulation layer 16 is formed on a face of the semiconductor substrate containing the bit line contact pad 14 and the storage node contact pad 13. The second insulation layer 16 is patterned to form the bit line contact 15. Then, the plurality of bit line stacks 20, which are connected with the bit line contacts 15 and have each spacer 20d on its sidewall, are formed. The bit line stack 20 is formed traversing the word line stack 8. The bit line stack 20 involves a bit line 20b and a bit line capping layer 20c laminated sequentially. Each of the bit lines 20b is electrically connected to the bit line contact pad 14 through the bit line contact 15. The bit line spacer 20d is formed on a sidewall of the bit line 20b and the capping layer 20c. A third insulation layer 18 is formed equally to a height of an upper part of the bit line capping layer 20c, on an entire face of the semiconductor substrate 2 containing the bit line stack 20 and the bit line spacer 20d. 
As shown in FIG. 3, the third insulation layer 18 and the second insulation layer 16 are continuously patterned to form the storage node contact 22 through a general method, so as to be connected to the storage node contact pad 12. Thus, the active regions 6s, 6d, the bit line contact pad 14, the storage node contact pad 13, the bit line stack 20, the word line stack 8, and the storage node contact 22 etc. constitute a straight lower structure.
As shown in FIG. 4, a buffer layer 24 is formed on the semiconductor substrate 2 having the storage node contact 22 was formed. The buffer layer 24 is formed with PE-TEOS (Plasma Enhanced Tetra Ethyl Ortho Silicate) material.
Referring to FIG. 5, a storage node of square type and a pad contact 26 for a connection with the node contact 22 are formed on the semiconductor substrate 2 having the buffer layer 24. The pad contact 26 is formed through procedures of forming an aperture through a photolithography process on the buffer layer 24, depositing the aperture with conductive material and then flattening it.
With reference to FIG. 6, an etch stop layer 28 and a molding oxide layer 30 are sequentially formed on the semiconductor substrate 2 having the pad contact 26, and thereon, an etch mask pattern is formed on the molding oxide layer 30. An opening part is formed to partially expose an upper part of the pad contact 26 connected with the storage node through an etch process. A CVD (Chemical Vapor Deposition) process is performed on an entire face of the semiconductor substrate, containing the opening part, to thus a conductive layer made of polysilicon. The conductive layer remained on the molding oxide layer is removed through a flattening process etc., to thus form the storage node 32 of the square type. The storage nodes of square type 32a through 32e each show a sectional face of the square type storage node shown in FIG. 1.
In the conventional processes described above, in order to form a storage node of square type on a semiconductor substrate based on a straight lower structure, a contact using a buffer layer is formed after forming the storage node contact. Thus, the storage node contact and the contact using the buffer layer, namely, two contacts, are formed between the storage node contact pad and the storage node that is connected from an upper part thereof. In other words, an additional procedure of forming a pad contact for connecting a storage node of square type and a storage node contact of straight structure with the buffer layer is required.
Furthermore, a critical photolithographic process should be accompanied with a contact forming process, thus a process margin is tight and an overall manufacturing process is relatively complicated and difficult.
Embodiments of the invention address these and other disadvantages of the conventional art.